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| NJU26103 Digital Audio Processor for TV General Description The NJU26103 is a high performance 24-bit digital audio processor for TV that has a QFP 32pins small package. The NJU26103 has an internal delay memory to adjust the output delay time for 2 channels audio signal. Moreover, the NJU26103 adopts SRS WOW technology. Package FEATURES * Variable 2 Channels Audio Delay. Maximum Delay 42msec (fs = 48kHz) * SRS WOW audio technology NJU26103 Digital Signal Processor Specification * 24bit Fixed-point Digital Signal Processing * Maximum Clock Frequency : 38MHz * Digital Audio Interface : 2 Input ports / 1 Output port * Two kinds of micro computer interface I2C Bus (standard-mode/100Kbps) 4-Wire Serial Bus (4-Wire: clock, enable, input data, output data) * Power Supply : DSP Core : 2.5V I/O interface: 2.5V(+3.3V tolerant) I/O interface: 2.5V(+3.3V tolerant) * Package : QFP 32pin * Note1: The SRS technology right incorporated in the NJU26103 are owned by SRS Labs, a U.S. Corporation and licensed to New Japan Radio Co., Ltd. SRS is protected under U.S. and foreign patents issued and / or pending. SRS, WOW and the are trademarks of SRS Labs, Inc. in the United States and selected foreign countries. Neither the purchase of the NJU26103, nor the corresponding sale of audio enhancement equipment conveys the right to sell commercialized recordings made with any SRS technology. SRS Labs requires that all users of the NJU26103 must enter into a license agreement directly with SRS Labs if the royalty is not Included in the purchase price. SRS Labs also requires any users to comply with all rules and regulations as outlined in the SRS Trademark Usage Manual. For further information, please contact: SRS Labs, Inc. 2909 Daimler Street. Santa Ana, CA 92705 USA Tel: 949-442-1070 2 Fax: 949-852-1099 http://www.srslabs.com * Note2: Purchase of I C components of New Japan Radio Co. ,Ltd or one of sublicensed Associated Companies conveys a license under the Philips I C Patent Rights to use these components in an I C system, provided that the system conforms to the I C Standard specification as defined by Philips. 2 2 2 -1- NJU26103 DSP Block Diagram Fig.1-1 NJU26103 Block Diagram AD1/SDIN AD2/SS NJU26103 DSP ARITHMETIC UNIT SERIAL AUDIO INTERFACE BCKO LRO 24-BIT x 24-BIT MULTIPLIER ALU L/R SDO0 SDI0 SDI1 C/LFE SDO1 BCKI SL/SR SDO2 LRI SCL/SCK SDA/SDOUT SERIAL HOST INTERFACE PROGRAM CONTROL RESETX MCK XI XO TIMING GENERATOR ADDRESS GENERATION UNIT DELAY RAM DATA RAM FIRMWARE ROM GPIO AND CONFIGURATION INTERFACE SEL1 DSP Function Diagram Fig.1-2 NJU26103 Function Diagram SDI_0 Lin SDI_0 Rin SDO_0 Lout D elay WOW SDO_0 Rout SDI_1 Lin SDI_1 Rin -2- NJU26103 Pin Configuration VDDR VDDR VDDC VDDC VSSR 24 VSSR 23 VSSC VSSC 22 21 20 19 18 17 SDI0 SDI1 TEST3 LRI BCKI MCK BCKO LRO 25 TEST2 VSSC VDDC RESETX VSSO XO XI VDDO 16 26 15 27 14 28 NJU26103 13 29 30 31 32 1 12 11 10 9 2 3 4 5 6 7 8 TEST0 TEST1 SDO0 SEL1 SCL/SCK SDA/SDOUT AD1/SDIN AD2/SSX Pin Description Table1-1 Pin Description No. Symbol I/O Description 1 TEST0 O OPEN 2 TEST1 O OPEN 3 SDO_0 O Audio Data Output 4 SEL1 I Select I2C or Serial bus 5 SCL/SCK I I2C Clock / Serial Clock 6 SDA/SDOUT IO I2C I/O / Serial Output 7 AD1/SDIN I I2C Address / Serial Input 8 AD2/SSX I I2C Address / Serial Enable 9 VDDO P OSC Power Supply +2.5V 10 XI I X'tal Clock Input 11 XO O X'tal Clock Output 12 VSSO G OSC GND 13 RESETX I RESET 14 VDDC P Core Power Supply +2.5V 15 VSSC G Core GND 16 TEST2 IO OPEN I:In, O:Out, IO:Bidir, P:+Power, G:GND No. 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Symbol VDDC VDDC VSSC VSSC VDDR VDDR VSSR VSSR SDI_0 SDI_1 TEST3 LRI BCKI MCK BCKO LRO I/O P P G G P P G G I I I I I O O O Description Core Power Supply +2.5V Core Power Supply +2.5V Core GND Core GND I/O Power Supply +2.5V I/O Power Supply +2.5V I/O GND I/O GND Audio Data Input Audio Data Input GND LR Clock Input CH0 Bit Clock Input CH1 Master Clock Output Bit Clock Output LR Clock Output -3- NJU26103 Absolute Maximum Ratings Table1-2 Absolute Maximum Ratings Parameter Supply Voltage Pin No.10(Xi) Input Voltage Input,Output Pin Voltage Power Dissipation Operating Temperature * Storage Temperature Symbol VDD Vx(OSC) Vx PD TOPR Tstg Rating 3.05 -0.33.05 -0.33.6 0.3 -20+75 -40+125 Units V V V W * For the car application, please ask NJR sale. Electric Characteristics Table1-3 Electric Characteristics (VDD=2.5V,Ta=25) Parameter Operating VDD Voltage Operating Current Recommended Operating Temperature High Level Input Voltage(Xi) High Level Input Voltage Low Level Input Voltage High Level Input Current High Level Input Current Low Level Input Current High Level Output Voltage Low Level Output Voltage Input Capacitance Input Rise/Fall transition Time Clock Frequency Ext.System Clock Duty Cycle Symbol VDD IDD TOPRR VIH(OSC) VIH VIL IIH IIH(pd) IIL VOH VOL CIN tr / tf fOSC rEC except for No.5, 6, 7, 8pin * No.10pin(Xi) No.10pin(Xi) VIN =3.3V VIN =3.3V VIN =VSS IOH=-2mA IOL=2mA Test Condition VDD pins fOSC=36.864MHz VDD =2.5V No.10pin(Xi) Only Min. 2.25 0 2.0 2.0 VSS -10 100 -10 VDD -0.4 47.5 Typ. 2.5 60 25 5 50 Max. 2.75 70 VDD 3.3 0.5 +10 300 +10 0.4 100 38.0 52.5 Units V mA V V V A A A V V pF ns MHz % * The tr / tf of these terminals is specified separately. * All input / input-and-output terminals serve as the Schmidt trigger input except for No.10pin(Xi). -4- NJU26103 1. Clock and Reset The NJU26103 Xi pin requires the system clock that should be related to the sample frequency fs. The Xi/Xo pins can generate the system clock by connecting the crystal oscillator or the ceramic resonator. Refer to the application circuit diagram about the circuit parameters. When the external oscillator is connected to Xi/Xo pins, check the voltage level of the pins. Because the maximum input voltage level of Xi pin is deferent from the other input or bi-directional pins. The maximum voltage-level of Xi pin equals to VDD. To initialize the NJU26103, RESET pin should be set low level during some period. After some period of Low level, RESET pin should be High level. This procedure starts the initialization of the NJU26103. To finalize the initialization procedure takes 1 m sec. After 1 m sec, the NJU26103 can accept a command from Host controller. The detail status of the initialized NJU26103 is referred to the each command that describes the initial status. To select I2C bus or 4-Wire serial bus, some level should be supplied to SEL1 pin. When SEL1="L", I2C bus is selected. When SEL1="H", 4-Wire serial bus is selected. The level of SEL1 is checked by the NJU26103 in 1 m sec after RESET-pin level goes to "H". After the power supply and the oscillation of the NJU26103 becomes stable, RESET pin should be kept Low-level at least tRESETX period. Vdd Xi OSC unstable OSC stable tRESETX RESETX Fig. 1-3 Reset Timing Table 1-4 Reset Time Symbol tRESETX Time 1us -5- NJU26103 2 System Clock Audio data samples must be transferred in synchronism between all components of the digital audio system. That is, for each audio sample originated by an audio source there must be one and only one audio sample processed by the NJU26103 and delivered to the D/A converters. To accomplish this, one device in the system is selected to generate the audio sample rate; the remaining devices are designated to follow this sample rate. The device that generates the audio sample rate is called the MASTER device; all devices following this sample rate are called SLAVE(s) LR, BCK and MCK should be synchronized. This is described in next section 2.1. When the NJU26103 is in MASTER mode, the NJU26103 system clock should be 768 multiples of the sampling frequency (Table2-1). When the NJU26103 is in SLAVE mode, NJU26103 system clock should be from 768 multiples of the sampling frequency to the maximum operating frequency. 2.1 Audio Clock Three types of clock signals are included in the serial audio interface. Two of the clock signals LR (LRI and LRO) and BCK (BCKI and BCKO) establish data transfer on the serial data lines. The third clock, MCK, is not associated with serial data transfer but is required by delta-sigma A/D and D/A converters. The frequency of the LR clock is, by definition, equal to the digital audio sample rate, Fs. BCK and MCK operate at multiples of the LR clock rate. Therefore the signals LR, BCK and MCK must be locked, that is, they must be generated or derived from a single frequency reference. In SLAVE mode, the NJU26103 dose not generate MCK clock. Table2- Sampling Frequency and BCK, MCK, Xi Clock Signal LR BCK(32fs) BCK(64fs) MCK(256fs) MCK(384fs) Xi Multiple Frequency 1Fs 32Fs 64Fs 256Fs 384Fs 768Fs 32KHz 32kHz 1.024MHz 2.048MHz 8.192MHz 12.288MHz 24.576MHz 44.1kHz 44.1kHz 1.4112MHz 2.822MHz 11.289MHz 16.934MHz 33.8688MHz 48kHz 48kHz 1.536MHz 3.072MHz 12.288MHz 18.432MHz 36.864MHz SDIx SDOx BCKI LRI BCKO LRO MCK CLOCK DIVIDER MAS TER SLAVE Xi Xo Oscillator Fig. 2-1 MASTER / SLAVE Mode -6- NJU26103 3. Audio Interface The serial audio interface carries audio data to and from the NJU26103. Industry standard serial data formats of I S, MSB-first left-justified or MSB-first right-justified are supported. These serial audio formats define a pair of digital audio signals (stereo audio) on each data line. Two clock lines, BCK (bit clock) and LR (left/right word clock) establish timing for serial data transfers. 2 The NJU26103 serial audio interface includes two data input lines; SDI0 and SDI1 and one data output line SDO0 as shown in the figure below. The input serial data is selected by the firmaware command. The NJU26103 has a pair of left/right clock lines (LRI and LRO) and a pair of bit clock lines (BCKI and BCKO). Clock inputs BCKI and LRI are used to accept timing signals from an external device when the NJU26103 is operating in SLAVE clock mode. The BCKO,LRO and system clock output MCK, is provided for delta-sigma A/D and D/A converters when the NJU26103 operates in MASTER mode. In SLAVE mode, the output of BCKO and LRO are the buffered output of BCKI and LRI. The output of MCK is fixed to low level in SLAVE mode. Fig. 3-1 Serial Audio Interface Serial Data Inputs SDI0 SDI1 SDO0 Serial Data Output NJU26103 Serial Clock Inputs BCKI LRI BCKO LRO MCK Serial Clock Outputs System clock for A/D, D/A converters (DSP MASTER mode only) -7- NJU26103 3.1 Audio Data Format The NJU26103 can exchange data using any of three industry-standard digital audio data formats: I2S, MSB-first Left-justified, or MSB-first Right-justified. The three serial formats differ primarily in the placement of the audio data word relative to the LR clock. Left-justified format places the most-significant data bit (MSB) as the first bit after an LR transition. I2S format places the most-significant data bit (MSB) as the second bit after an LR transition (one bit delay relative to left-justified format). Right-justified format places the least-significant data bit (LSB) as the last bit before an LR transition. Clock LR (LRI, LRO) marks data word boundaries and clock BCK (BCKI, BCKO) clocks the transfer of serial data bits. One period of LR defines a complete stereo audio sample and thus the rate of LR equals the audio sample rate (Fs). All formats transmit the stereo sample left channel first. Note that polarity of LR is opposite in I2S format (LR:LOW = Left channel data) compared to Left-Justified or Right-Justified formats. The number of BCK clock must follow the serial data format. If the BCK clock is not enough , the right sound are not produced. Set serial data format for the adequate mode that A/Ds ,D/As or Codecs reqire. The NJU26103 supports serial data format which includes 32(32fs) or 64(64fs) BCK clocks. This serial data format is applied to both MASTER and SLAVE mode. 3.2 LRI, LRO BCKI, BCKO M SB Serial Audio Data Transmitting Diagram Left Channel Right Channel LSB 32 Clocks M SB 32 Clocks LSB 23 SDI, SDO 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Fig. 3-2 Left-Justified Data Format 64Fs, 24bit Data LRI, LRO BCKI, BCKO M SB LSB 32 Clocks M SB 32 Clocks LSB Left Channel Right Channel SDI, SDO 2 1 0 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Fig. 3-3 Right-Justified Data Format 64Fs, 24bit Data LRI, LRO BCKI, BCKO M SB LSB 32 Clocks M SB 32 Clocks LSB Left Channel Right Channel SDI, SDO 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Fig. 3-4 I2S Data Format 64Fs, 24bit Data -8- NJU26103 LRI, LRO BCKI, BCKO M SB LSB 32 Clocks M SB 32 Clocks LSB 19 Left Channel Right Channel SDI, SDO 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Fig. 3-5 Left-Justified Data Format 64Fs, 20bit Data LRI, LRO BCKI, BCKO M SB LSB 32 Clocks M SB 32 Clocks LSB Left Channel Right Channel SDI, SDO 2 1 0 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Fig. 3-6 Right-Justified Data Format 64Fs, 20bit Data LRI, LRO BCKI, BCKO M SB LSB 32 Clocks M SB 32 Clocks LSB Left Channel Right Channel SDI, SDO 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Fig. 3-7 I2S Data Format 64Fs, 20bit Data LRI, LRO BCKI, BCKO M SB Left Channel Right Channel LSB 32 Clocks M SB 32 Clocks LSB 17 SDI, SDO 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Fig. 3-8 Left-Justified Data Format 64Fs, 18bit Data LRI, LRO BCKI, BCKO M SB Left Channel Right Channel LSB 32 Clocks M SB 32 Clocks LSB SDI, SDO 2 1 0 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Fig. 3-9 Right-Justified Data Format 64Fs, 18bit Data -9- NJU26103 LRI, LRO BCKI, BCKO M SB LSB 32 Clocks M SB 32 Clocks LSB Left Channel Right Channel SDI, SDO 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Fig. 3-10 I2S Data Format 64Fs, 18bit Data LRI, LRO BCKI, BCKO M SB Left Channel Right Channel LSB M SB 16 Clocks 16 Clocks LSB SDI, SDO 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Fig. 3-11 Left-Justified Data Format 32Fs, 16bit Data LRI, LRO BCKI, BCKO M SB Left Channel Right Channel LSB M SB 16 Clocks 16 Clocks LSB SDI, SDO 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Fig. 3-12 Right-Justified Data Format 32Fs, 16bit Data LRI, LRO BCKI, BCKO M SB Left Channel Right Channel LSB M SB 16 Clocks 16 Clocks LSB SDI, SDO 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Fig. 3-13 I2S Data Format 32Fs, 16bit Data - 10 - NJU26103 3.3 Serial Audio Timing Table 3-1 Serial Audio Input Timing Parameters Parameter BCKI Frequency BCKI Period L Pulse Width H Pulse Width BCKI to LRI Time LRI to BCKI Time Data Setup Time Data Hold Time Symbol Test Condition Min 0.9 tSIL tSIH TSLI tLSI tDS tDH 85 85 40 40 40 40 Typ. Max 4.0 Units MHz ns ns ns ns ns LRI tSIH tSIL tSLI tLSI BCKI tDS tDH SDI0,1 Fig. 3-14 Serial Audio Input Timing - 11 - NJU26103 Table 3-2 Serial Audio Output Timing Parameters Parameter BCKO Period L Pulse Width H Pulse Width BCKO to LRO Time LRO to BCKO Time Data Output Delay Symbol tSOL tSOH tSLO tLSO tDOD Test Condition CL:LRO, BCKO, SDO=25pF Min tSIL-40 tSIH-40 20 20 Typ. Max tSIL+40 tSIH+40 20 Units ns ns ns ns LRO tSOH tSOL tSLO tLSO BCKO tDOD SDO0,1,2 Fig. 3-15 Serial Audio Output Timing - 12 - NJU26103 4. Host Interface The NJU26103 can be controlled via Serial Host Interface (SHI) using either of two serial bus format : 4-Wire serial bus or I2C bus. Data transfers are in 8 bit packets (1 byte) when using either format. The SHI operates only in a SLAVE fashion. A host controller connected to the interface always drives the clock (SCL / SCK) line and initiates data transfers, regardless of the chosen communication protocol. The SEL1 pin controls the serial bus mode. When the SEL1 is low during the NJU26103 initialization, 4-Wire serial bus is available. When the SEL1 is high during the NJU26103 initialization, I2C bus is available. Table 4-1 Serial Host Interface Pin Description Serial Clock Serial Data SDA/SDOUT 6 Serial Data Output (Bi-directional) AD1/SDIN 7 Serial Data Input I2C bus address Bit1 AD2/SSx 8 SLAVE Select I2C bus address Bit2 Note : SDA /SDOUT pin is a bi-directional open drain. When 4-Wire Serial bus is selected, and SSX is effective, and a CMOS output and SSX are invalid, it will be in a Hi-Z state. This pin, which is assigned for 4-Wire serial bus format or for I2C , requires a 4.7k pull-up resister. Symbol 2 (I C / Serial) SCL/SCK Pin No. 5 4-Wire Serial bus Format Serial Clock I2C bus Format 4.1 4-Wire Serial Interface The serial host interface can be configured for 4-Wire Serial bus communication by setting SEL1="H" during the Reset Sequence initialization. SHI bus communication is full-duplex; a write byte is shifted into the SDIN pin at the same time that a read byte is shifted out of the SDOUT pin. Data transfers are MSB first and are enabled by setting the Slave Select pin LOW (SSX = 0). Data is clocked into SDIN on rising transitions of SCK. Data is latched at SDOUT on falling transitions of SCK except for the first byte (MSB) which is latched on the falling transitions of SSX. SDOUT is Hi-Z in case of SSX = "H". SDOUT is CMOS output in case of SSX = "L". SDOUT needs a pull-up resistor when SDOUT is Hi-Z. - 13 - NJU26103 Table 4-2 4-Wire Serial Interface Timing Parameters Parameter Input Data Rising Time Input Data Falling Time Serial Clock Rising Time Serial Clock Falling Time Serial Strobe Rising Time Serial Strobe Falling Time Serial Clock H Duration Serial Clock L Duration Serial Clock Period Serial Strobe Setup Time Serial Strobe Hold Time Serial Strobe L Duration Serial Strobe H Duration Input Data Setup Time Input Data Hold Time Output Data Delay (From SSx) Output Data Delay (From SCK) Output Data Hold Time Output Data Turn off Time (Hi-Z) a SDIN Symbol tMSDr tMSDf tMSCrw tMSCf tMSSr tMSSf tMSCa tMSCn tMSCc tMSSs tMSSh tMSSa tMSSn tMSDis tMSDih tMSDos tMSDo tMSDoh tMSDov Timelines a-b a-b d-e f-g p-q m-n e-f g-h e-i n-e j-q n-p q-r b-e e-c n-o,CL=25pF g-k(data-6), CL=25pF g-k(data-7) q-l Min. 50 50 250 100 30 40 20 20 0 - Typ. - 1.0 Max. 100 100 100 100 100 100 50 50 40 Units ns ns ns ns ns ns ns ns ns ns ns s ns ns ns ns ns ns ns - b c 7 d ef 6 gh i 5 1 0 j SCK SDOUT Hi-Z m n o 7 k 6 5 1 0 Note (3) Hi-Z l SSx MSB LSB p q r Fig. 4-1 4-Wire Serial Interface Timing Note : *1 When the data-clock is less than 8 clocks, the input data is shifted to LSB side and is sent to the DSP core at the transition of SSX="H". *2 When the data-clock is more than 8 clocks, the last 8 bit data becomes valid. *3 After sending LSB data, SDOUT transmits the MSB data which is received via SDIN until SSX becomes "H". *4 SDOUT is Hi-Z in case of SSX = "H". SDOUT is CMOS output in case of SSX = "L". SDOUT needs a pull-up resistor to prevent SDOUT from becoming floating level. - 14 - NJU26103 4.2 I2C Bus When the NJU26103 is configured for I2C bus communication in SEL1="L", the serial host interface transfers data on the SDA pin and clocks data on the SCL pin. SDA is an open drain pin requiring an external 4.7k pull-up resistor. Pins AD1 and AD2 are used to configure the seven-bit SLAVE address of the serial host interface. This offers additional flexibility in a system design by offering two different possible SLAVE addresses for which the NJU26103 will respond to. An address can be arbitrarily set up with an internal setup and this AD1 terminal. In the NJU26103, AD2 pin should be connected to "H". Any I2C address could be chosen for AD1. The I2C address of AD1 is decided by connection of AD1-pin. The I2C address should be the same level of AD1-pin . Table 4-3 I2C Bus SLAVE Address bit7 bit6 bit5 Bit4 Bit3 bit2 bit1 bit0 1 2 0 0 1 1 1 AD2* AD1* R/W 2 *1 AD2 pin should be connected to high. The I C address of AD2 should be 1. *2 SLAVE address is 0 when AD1 is L. SLAVE address is 1 when AD1 is H. The figure on the following page shows the basic timing relationships for transfers. A transfer is initiated with a START condition, followed by the SLAVE address byte. The SLAVE address consists of the seven-bit SLAVE address followed by a read/write (R/W) bit. When an address with an effective serial host interface is detected, the acknowledgement bit which sets a SDA line to LOW in the ninth bit clock cycle is returned. The R/W bit in the SLAVE address byte sets the direction of data transmission until a STOP condition terminates the transfer. R/W = 0 indicates the host will send to the NJU26103 while R/W = 1 indicates the host will receive data from the NJU26103. SDA 1-7 8 9 1-7 8 9 SCL S Start Address R/W ACK Data ACK P Stop Fig. 4-2 I2C Bus Format In case of the NJU26103, only single-byte transmission is available. The serial host interface supports "Standard-Mode (100kbps)" I2C bus data transfer. - 15 - NJU26103 Table 4-4 I2C Bus Interface Timing Parameters Parameter SCL Clock Frequency Start Condition Hold Time SCL "L" Duration SCL "H" Duration Start Condition Setup Time Data Hole Time Data Setup Time Rising Time Falling Time Stop Condition Setup Time Bus Release Time Symbol fSCL tHD:STA tLOW tHIGH tSU:STA tHD:DAT tSU:DAT tR tF tSU:STO tBUF Standard Mode Min Max 0 100 4.0 4.7 4.0 4.7 0 3.45 250 1000 300 4.0 4.7 Units kHz s s s s s ns ns ns s s SDA tBUF SCL tR tF tHD:STA tHD:STA P S tLOW tHD:DAT tHIGH tSU:DAT Sr tSU:STA tSU:STO P Fig. 4-3 I2C Bus Timing - 16 - NJU26103 5. Firmware Command Table Host processor can control the NJU26103 through I2C bus or 4-Wire Serial Bus. The next table shows the command to control the NJU26103. Table5-1 NJU26103 Command List No. Command 1 Fs 2 Input Select 3 Mode Select 4 WOW 5 TruBass 6 Delay Time 7 Program Mode 8 Through Output 9 WOW Output Trim 10 TruBass 11 Stereo Width 12 System State 13 Firmware Version 14 NOP Command Description Select the sampling frequency : 32/ 44.1/ 48KHz Select digital audio input Select mode : Mute, Thru, WOW Select WOW parameters : Bit rate, Focus, Input mode Select TruBass Speaker size Set Delay time Select mode : Stereo, TruBass, Focus, Delay Trim Through output level Trim WOW output level TruBass Control Stereo Width Control Set System parameters : Digital Audio Format Check Firmware Version Check DSP condition - 17 - NJU26103 Package Dimensions (Package Code : QFP32-R1) Version V2.2 [CAUTION] The specifications on this databook are only given for information , without any guarantee as regards either mistakes or omissions. The application circuits in this databook are described only to show representative usages of the product and not intended for the guarantee or permission of any right including the industrial rights. - 18 - |
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